[Open-graphics] OpenCores and fixing the wishbone problem

[Peter TB Brett]

On Friday 18 August 2006 02:50, Timothy Miller wrote:
> On 8/17/06, Attila Kinali <attila at kinali.ch> wrote:
> > Actualy, no. OGP is only a sideeffect of the openhardware movement.
> > I'd rather say that opencores is currently the center. Though,
> > opencores has a different aproach. They do not produce hardware but
> > collect HDL code for public use. Ie try to be something like SF
> > and freshmeat for the hardware guys.
>
> Speaking of OpenCores, I was thinking that we might try to fix the one
> major blemish I think they have, called wishbone.  It's a
> bus/interface protocol they have defined so that any of their designs
> can communicate with any of their other designs.  I'm sure someone
> will want to argue with me, but based on what I've read about the
> protocol, it is not designed for speed.  The protocol requires a long
> combinatorial path for the "busy" signal that prevents
> high-performance designs.  Either you have a slow clock because of the
> long logic path, or you have a high clock rate but transfer data only
> every other clock cycle.

What about using Wishbone components that support Registered Feedback Bus 
Cycles?  Pages 69-71 of the B.3 spec seem to indicate that the RFB WISHBONE 
mode was specifically designed to overcome the exact deficiencies of WISHBONE 
Classic to which you refer.

Peter



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