[Open-graphics] OpenCores and fixing the wishbone problem

[Peter TB Brett]

On Friday 18 August 2006 14:08, Timothy Miller wrote:
> On 8/18/06, Peter TB Brett <peter at peter-b.co.uk> wrote:
> > What about using Wishbone components that support Registered Feedback Bus
> > Cycles?  Pages 69-71 of the B.3 spec seem to indicate that the RFB
> > WISHBONE mode was specifically designed to overcome the exact
> > deficiencies of WISHBONE Classic to which you refer.
>
> I had read that, and IIRC, that's the mode that can transfer data only
> every other clock cycle.

This is incorrect.  I refer you to table 4-1 on page 70 of the spec.

  For a burst transfer of 32 data words:

  Classic cycle with asynchronous termination: 32 clocks
  Classic cycle with synchronous termination: 64 clocks
  RFB cycle with synchronous termination: 33 clocks

You may be confused in that a RFB bus master _can_ do Classic cycles if 
necessary, hence Figure 4-5 which shows two clock cycles to transfer a single 
word.  But contrast for example Figure 4-8 (page 86): it clearly shows one 
word being transferred per clock cycle.

Peter

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