[Open-graphics] Entirely rewritten LaTeX timing diagram... um... thing

[Timothy Miller]

On 12/25/06, Daniel Rozsnyó <daniel at rozsnyo.com> wrote:
> Cant you just embed .SVG into TeX ? Then you can do the vector graphics
> by some translation software from a more semantic description of your
> diagram (and/ore from an simulation output)

To me, it's a pain in the neck to use two programs to do one thing.  I
just want to type it all into one document.

I also think it's a pain when you can't enter some constraint directly
into the Verilog code.  For instance, if I want to constraining the
timing on a path between two registers, Xilinx tools require that I
enter the constraint into a separate file.  I HATE that.

-- 
Timothy Miller
http://www.cse.ohio-state.edu/~millerti