[Open-graphics] video head 0 module template

[Timothy Miller]

On 10/5/06, Simon Persson <simper-2 at student.ltu.se> wrote:
> On Thursday 05 October 2006 19:52, you wrote:
> > On 10/5/06, Simon Persson <simper-2 at student.ltu.se> wrote:
> > > On Monday 02 October 2006 23:32, Timothy Miller wrote:
> > > > // Since this is a DDR interface, it is convenient to use a DDR FF
> > > > // to provide the clock signal.  IIRC, we want data0 to appear with
> > > > // the rising edge of the clock, so we want to produce it on the
> > > > // negative edge.
> > > > ddrff1 ff0 (.Q(dvi_m_clk), .C0(clock), .C1(~clock), .D0(1'b0),
> > > > .D1(1'b1), .OE(1'b1));
> > > > ddrff1 ff1 (.Q(dvi_s_clk), .C0(clock), .C1(~clock), .D0(1'b0),
> > > > .D1(1'b1), .OE(1'b1));
> > >
> > > I'm not sure I understand the purpose of these... As I see it they only
> > > invert and add a slight delay.
> >
> > What they do logically is just transfer different data on opposing
> > edges of the clock.  But a normal register cannot behave this way.
> > Xilinx has supplied special I/O registers that are DDR-capable, and we
> > have to manually instantiate them.
> >
>
> Yep, understand that. I was thinking more about why we need a flipflop at
> all... Now I looked it up in the spartan 3 data sheet and it says that this
> is a way to minimise skew between data and clock. (which was the explanation
> I expected, asked here to be sure)

Exactly.  Without explicit constraints, the timing from an internal
net to a pin is unpredictable.  If you make sure to use the registers
in the I/O buffers, you mostly eliminate the variance between
different pins on the same bus.

> I also remember getting a warning once when I brought out  a clock net to a
> pin, is that related to this?

Not sure why you got the warning, but using the DDR FF to generate the
clock allows you to time it exactly relative to any data the clock may
be associated with.

>
> I'm attaching the design along with a simple testbench. Feedback would be
> appreciated, I only learned verilog this summer so I'm sure there are things
> to improve.

I may need a reminder that it's there.  I want to look at it, but
can't right now.  Also, since others are working on the same problem,
I hope they'll have a look at combine designs.