I had a quick glance. Looks nice. I suggest, instead of changing the ddrff definition in the synthesizable part, add this code to your test bench: module FDDRRSE(Q, C0, C1, CE, D0, D1, R, S); output Q; reg Q; input C0, C1, CE, D0, D1, R, S; always @(posedge C0) Q <= D0; always @(posedge C1) Q <= D1; endmodule