[Open-graphics] Center for High-Performance Reconfigurable Computing

[Arnaud Boulan]

Quoting Timothy Miller <theosib at gmail.com>:

> On 10/15/06, William DUCK <guillaume.fortaine at wanadoo.fr> wrote:
>
>>
>> NSF Center for High-Performance Reconfigurable Computing (CHREC)
>>
>
> This is a long-term sort of project idea for us.  The holy grail would
> be to convert arbitrary C or Fortran code into FPGA logic.  (This
> would be especially good for Cray computers that arrange Opterons with
> Xilinx FPGAs.)  A more realistic goal, however, would be to convert a
> restricted subset of C into gates.


Hello,

This is the first time I post here, even though I have been following  
OGP development for a long time. So first i'd like to thank everyone  
involved in OGP for their great job.

Now, regarding high level synthesis:
In the university where I learned hardware design, there is such a  
project that is beeing developped. You can have a look at it here:
http://www-asim.lip6.fr/recherche/disydent/doc.html
"Disydent" (Digital System Design Environment) is a framework for  
co-design of embedded systems. In this framework, an application is  
described as a set of modules communicating through FIFOs. Each  
modules is written in a subset of the C language, and these modules  
can be either run in software directly, or synthezised as a hardware  
coprocessor with the "ugh" (user guided high level synthesis) tool

Here is an example of what such a module would look like:

  /*** HCF EXAMPLE ***/
  #include <ughc.h>

  /*** channels ***/
  ugh_inChannel21 ina;
  ugh_inChannel21 inb;
  ugh_outChannel21 outa;

  /*** registers ***/
  uint21 a;
  uint21 b;

  /*** behavior ***/
  void hcf()
  {
    while (a!=0)
     if (a<b)
       b -= a;
     else
       a -= b;
  }

  void ugh_main(void)
  {
    for ( ;; ) {
      ugh_read(ina,&a);
      ugh_read(inb,&b);
      hcf();
      ugh_write(outa,&a);
    }
  }

  /*** HCF END EXAMPLE ***/

Taking this (and a file describing constraints on the datapath) as an  
inmput, the hardware synthetizer is able to generate the datapath and  
fsm implementing the module at a given clock period.

"Disydent" is publicly available and distributed under the GPL  
license, so if you like you can try to play with it :)
If you have any questions about this tool, do not hesitate to ask.

Arnaud