[Open-graphics] Video head 0 test logic

[Attila Kinali]

Moin,

Also a small comment from my side on a very common mistake:

On Tue, 17 Oct 2006 13:14:44 -0400
"Timothy Miller" <theosib at gmail.com> wrote:

> always @(posedge clock or posedge reset) begin
>     if (reset) begin
[reset code]
>     end
>     else begin
[functional code]
>     end
> end


Please do not use asynchrone resets. Using asynchrone
resets will in nearly all cases violate the setup and
hold times. Even using a asynchron edge trigered reset
like here, does only solve the hold time problem.
The setup time violation is still there.
Violation of either setup or hold time will result
in a metastable behavior of the registers.

Ok, one can argue now that reset will be asserted
for more than one clock cycle anyways, so after
the next rising edge of the clock all metastable
register will settle into the reset state. But,
there will be a period of time (up to one clock period)
in which more or less random signals are produced.
Those signals can disturb anything that they are concted
to. Especialy devices that are connected to our chip, and
if bad comes to bad you could fry something.


				Attila Kinali

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