[Open-graphics] Rewritten memctl, please test for regression.

[Timothy Miller]

If you're watching the memory controller, you'll notice that I've
added an alternate state machine.  I couldn't get the older one (that
is logically correct) to synthesize to be fast enough, so I'm trying
another design.  It too is logically correct, and I'm about to see if
I can optimize it for speed successfully.  I could use some help with
regression testing.

One drawback of the latest fsm is that it inserts a min of two cycles
between certain bus commands.  I'm pretty sure that doesn't matter,
because I'm pretty sure most timing numbers are going to require at
least two delay cycles (when demands on the memory controller are
constant).  Please check to make sure I'm not wrong on that.