[Open-graphics] Help with memory timing numbers?

[Timothy Miller]

Finally, I have a memory controller design that both works and is
potentially capable of running at the speed I want it to run at.  (By
potentially, I mean that the only critical paths are ones that have
zero levels of logic and are therefore subject purely to placement and
routing.)

As one last optimization before I check it all in, I was hoping that
people could give me an idea as to the minimum and maximum ranges on
timing numbers.

The timing numbers for this controller aren't _exactly_ the same as
what you read in the spec, where you see things like tRAS.  For one
thing, those numbers are mostly in nanoseconds, and secondly, some of
the timing numbers that are in clocks don't have EXACTLY the same
semantics (e.g. when they say "1 tCK" they mean back-to-back, where
for me, that's zero, as in zero dead cycles.)

Here are the timing variables:

    r2w_wait,
    w2r_wait,
    act2rw_wait,
    w2pre_wait,
    r2pre_wait,
    pre2act_wait,
    act2pre_wait,
    refresh2act_wait,
    cas_latency,

For each of these, zero means that there are zero idle cycles between
the two commands.  1 means there is one idle cycle, etc.  They're all
in clock cycles.

For minimum numbers, consider DDR memories running at 133Mhz (DDR300).
 133Mhz has a cycle period of about 7.5ns.

A timing parameter that requires a delay of 70ns would require
ceil(70/7.5) = 10 cycles delay.  I chose that example to represent
tRFC for the Samsung part we're using right now.  That 70 ns
represents the time delay between the center of the refresh command
and the center of the precharge command, which for us is 9 idle
cycles, so we need a value of 9.

For the maximum numbers, consider the fastest DDR part you can get.
Considering that DDR2 is overtaking DDR, don't expect the fastest DDR
parts to get much faster, so just pick the fastest you can find.  If
DDR667 is the fastest you can find, then that has a clock rate of
333Mhz or a period of 3 ns.  The 70ns tRFC would then be ceil(70/3) =
24 cycles.  Our variable would then need a value of 23 for the number
of idle cycles.

You get the idea.

Thanks.