[Open-graphics] fifos and metastability

[James Richard Tyrer]

Timothy Normand Miller wrote:
> I've posted to SVN a new fifo design.  It's kinda wasteful, but it's
> designed for very high clock rates.  It's an async fifo (meaning that
> the two ends are on different clocks), and the cross-domain
> communitation is one-hot (rather than gray-coded).
> 
> When I posted the original one, someone was kind enough to perform an
> analysis to determine if RAM contents would also suffer from
> metastability.  I think this one will have the same problem, so I was
> hoping that same kind person would please have a look at this one.
> 
> https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/fifos/onehot_fifo_32.v 
> 
OT comment: Again, I wish that this was as simple as designing with 
parts.  IIRC, a SR latch made with Schmidt-Trigger input gates can not 
enter a metastable state because it is in the hysteresis loop (where the 
signal can never go).  You still have a problem of short pulses (when 
one clock goes high almost exactly [< 2 gate delays] when the other 
clock goes low) which must be dealt with (PLLs address this by adding 
more states to the ASM), but you can make a ASM with 4 gates which does:

    C1 | C2 | Out
   ____|____|____
            |
    0    0  |  0
    0    1  |  *
    1    0  |  *
    1    1  |  1

   * Out doesn't change from previous level

which was commonly use for clock synchronization.

Does the FPGA have a macro for a clock synchronization?  Specifically, 
the zero phase PLL detector macro might be adapted.

-- 
JRT