[Open-graphics] Synthesizing oga1hq

[Andre Pouliot]

2007/8/12, Timothy Normand Miller <theosib at gmail.com>:
>
> I've checked in some changes to hq.  There are a few bug fixes and
> also a hack to add an input port and an output port as synthesis
> placeholders.
>
> So, we have some synthesis results.  The winner is:  The multiplier.
> To make a 32x32 multiplier, four of the 18x18's have to be bolted
> together, and this is what we get:
>
> Slack:                  -12.191ns (requirement - (data path - clock




Too much multiply and add logic.  We want 10ns, but we're getting
> 22ns.  We need to think about ways to either stretch the pipeline, run
> the multiply as a parallel pipeline, or use fewer bits in the
> multiplier and/or multiplicand.


 Another possibility is to create a device that do the multiply like
coproccesor that isn't part of the ALU but is memory mapped in direct
adressing(if the nanocontroller support direct and indirect adressing). It
would look like 4 adressable register  2 for the input value and 2 for the
result. If something like this is done the multiply could be pipelined as
long as wanted and while waiting for the result other operations would be
possible and wouldn't lock the alu.
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