[Open-graphics] Multipliers in oga1hq

[Farhan Mohamed Ali]

Updated radix-4 multiplier attached. This one has zero detection so if 
either input is a zero then it will only take 2 cycles to complete. Uses 
a bit more logic but speed is not degraded from my testing (still 
120MHz). Hopefully Mark's results will agree with mine :)

The other question is, is this even beneficial? I seem to recall that 
zeros occur quite commonly. Even in the MIPS ISA, r0 is just a hardwired 
zero because of this if i remember right... so that is my justification 
for doing this.


On Fri, August 31, 2007 1:27 pm, Timothy Normand Miller said:
> That's a great page, Mark.  There's a lot you can see there too, like it
> demonstrates clearly things about routing, especially to/from pins.
> 
> As for Xilinx, I think I've kinda gotten used to it over time.  I have 
> adapted my coding style so that I am more likely to get the logic I 
> intend.  In general, the rule of thumb I apply to chip design is that the
> more you try to make the synthesizer infer (rather than telling it 
> directly), the more likely you are to get suboptimal results.  In order
> to be able to complete a design in a reasonable time, you have to strike
> a balance.  I use the synthesizer and timing analysis as a profiler, so I
> know where to concentrate my optimization effort.
> 
> On 8/31/07, Farhan Mohamed Ali <farhan at cmu.edu> wrote:
>> Thanks! So it seems to me like this compiler is a bit more consistent 
>> than the xilinx one. On xilinx i get rather different timing and 
>> utilization results between v2 and v3, even though they are logically
>> the same.
>> 
>> On Fri, August 31, 2007 11:19 am, Mark said:
>>> I've posted a run-down of the multipliers so far (any important ones
>>>  missing?) at http://jarvin.net/opengraphics/.  This includes photos
>>> of the most critical path post-PAR. 
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>> 
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> 
> 
> -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open
> Graphics Project
> 
> 
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