[Open-graphics] Clock generation

[James Richard Tyrer]

James Richard Tyrer wrote:
> It appears that the solution to the jitter problem might be to change 
> the way that we generate the clocks.
> 
> Something like this could be used to generate the existing two clocks 
> plus a third one to drive the pixel clock generators:
> 
> http://focus.ti.com/lit/ds/symlink/cdcel937.pdf
> 
> This is EEPROM (1K cycles) so it can't be used for the pixel clock 
> generators.
> 
> For the pixel clock generators, the maximum frequency required and 
> output voltage required are going to be the main parameters to choose 
> parts.
> 
To add to this.  If, we use a frequency synthesizer for the pixel 
clocks, it might actually be less expensive since the PLL's phase 
detector would operate at a much lower frequency.


The NXP (Phillips) 3xDAC has a maximum frequency of 330MHz as does the 
SiI1178.  If we are going to use a pixel clock that fast, there aren't 
many dot clock generators that are that fast.  200 to 230MHz seems to be 
the upper limit for most chips.

I found a Phillips part that we might want to look at:

http://www.nxp.com/pip/PCK12429_3.html

I'm not well today so someone else will have to look at it.

I also found an IDT chip but it is 5 volt.

If we are going to de-jitter, we should probably look at RF parts.

-- 
JRT