[Open-graphics] OGA1 mad dash: What's left

[Timothy Normand Miller]

On 12/30/07, Farhan Mohamed Ali <farhan at cmu.edu> wrote:
>
>     // Config regs and load mode register (lmr)
>     reg [14:0]             lmr_data;
>     reg [3:0]              lmr_delay;
>     reg                            lmr_addr;
>     reg [10:0]             refresh_delay;
>     reg                            refresh_enable;
>     reg [1:0]              lmr_write; // missing, added
> ***is the lmr_write reg only 2 bits?***

There should no longer be an lmr_write register.  I think you're
looking at an old version.  You might want to update and look again.

> ***does the right shift do anything here? seems to me like it's just
> copying back the same value***

It's a shift register.  The idea is to assert a signal in the bridge
clock domain that we can pick up without glitching in the memory clock
domain.  So what we do is sustain a signal for some number of clocks
and look for the transition in the other clock domain.

> ***the value of lmr_delay doesn't seem to change from 4'b1110, so do_lmr
>   value doesn't change? is there a shift register missing?***

That's the issue with having an out-of-date version.  :)

-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project