[Open-graphics] Challenges with async fifo designs holding up OGD1

[Jared Putnam]

--- Timothy Normand Miller <theosib at gmail.com> wrote:
> On 2/13/07, James Richard Tyrer <tyrerj at acm.org> wrote:
> > Timothy Normand Miller wrote:
> > > Understood.  We'd just like to avoid wasting a block RAM for a
> > > one-bit-wide fifo.
> > >
> > You don't think that you could do it in logic? rather than RAM.
> 
> That's even tighter.  Under the circumstances, wasting a block RAM is
> the better solution.  We'd just like a more elegant solution.

Can the pointer comparison be pipelined?  That is, the write pointer
would be compared against the next read pointer instead of[1] the
current one.  That way, it would be acceptable for there to be a delay
of one clock before the a halt signal could reach the writer.

It would likely be complicated, but I'm just throwing ideas out,
though.


[1] More likely "as well as" instead of "instead of", though.



 
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