[Open-graphics] Challenges with async fifo designs holding up OGD1

[Simon]

On 2/14/07, Timothy Normand Miller <theosib at gmail.com> wrote:
> On 2/13/07, James Richard Tyrer <tyrerj at acm.org> wrote:
> > How much simpler it is to think in terms of discrete parts. :-)
>
> Yeah.  If this were an ASIC, it would be a whole different story.
>

Sorry for going off topic, but is it feasible and sensible to
implement it both ways, depending on whether the target is an ASIC or
an FPGA, and then test both, to save some real estate on the ASIC?