[Open-graphics] A really good immediate use for OGD1: PCI bus analyzer

[Patrick McNamara]

Timothy Miller wrote:
> On 1/2/07, Patrick McNamara <wpmcnamara at yahoo.com> wrote:
>
>> Deep pipelines are your friend.  :)
>>
>> Actually, they 3S4000 really should do little more than pass the data
>> through.  Obviously, it needs to handle the RAM refresh, but beyond
>> that, in capture mode, I would argue that all it really needs to do is
>> track the memory location for the next sample and act as a pass through
>> for the bus samples.  There is no need to read from the memory during
>> capture and there is likely no need to write to it during upload.  Any
>> processing or program store for an embedded core should use the
>> DRAM/BRAM available in the 3S4000.  Since I don't think we will be gate
>> limited in either FPGA, brute force is a perfectly viable option.
>> Function over form as it were.
>
> The number of pins between the XP10 and the 3S4000 is about 40.  At
> 200MHz transfer rate, we thought we'd have a large data eye for the
> I/O receivers, but we don't.  That doesn't bode well for higher clock
> rates.
>
> Now, the thing is, at 400MHz, very little changes from clock to clock,
> because the PCI bus just doesn't transition that fast.  We're
> guaranteed to get LOTS of repetition in the signal, which means a RLE
> compression between the chips is very doable.
>
>
The problem here is the timing of the individual bus signals.  Assume
you are sampling at 330MHz.  That gives you 10 samples per PCI clock on
a 33MHz bus.  Each of the data and address lines may have slightly
different setup times.  It is quite possible that you will get a change
in your sample data in a majority of your sample windows, especially if
you are stepping the bus.  You will get a lot a repetition on a fairly
idle bus, but where it counts, at the beginning of the bus setup when
you need to make sure you have the timing right, you will get a lot a
change and need to be able to transfer a lot of data quickly.

In the worst case you probably need to be able to transfer around 112
bits per sample window:  32 bits or so for a time stamp and 80 or so for
PCI bus data.  That assumes that all bits change in a single sample
period.  Thats 3.5 32bit words that need to go between the two FPGAs in
a single 330MHz clock cycle.  Ouch.

Patrick M