[Open-graphics] Prototype app to look at: A hardware IDE [release early, release often]

[Koen De Vleeschauwer]

On Jul 1, 2007, at 10:09 PM, Timothy Normand Miller wrote:

> For some time now, I have been tinkering with the idea of developing a
> hardware IDE of sorts to help with chip design projects.  Like with
> many sort of programming tasks, there are tedious and error-prone
> aspects of coding Verilog, and I thought it would be nice to have a
> tool that would take care of many of these things for me.  There are
> some tools already to do this (e.g. Renoir), but they're expensive and
> not Free Software.
>
> One of the most bothersome problems with Verilog is with gluing
> modules together.

 From http://www.asics.ws/tools_sub.html:

TopGen is a perl script that takes one or more Verilog Modules and  
connects them together in a newly generated top level module. It can  
take a top level module prototype as an optional input as well.  
Further it supports aliases where signals with different names in the  
modules are connected together on the top level using a common signal  
name. Automatic width specification is also performed. The resulting  
top level will most likely still require manual editing, but 99% of  
the tedious copy, paste and typing work is eliminated.

regards,

koen