[Open-graphics] code question(s)

[Simon]

>From the diff:

Index: rtl/vid_ctl/vid_control.v
===================================================================
--- rtl/vid_ctl/vid_control.v	(revision 141)
+++ rtl/vid_ctl/vid_control.v	(working copy)
@@ -252,16 +252,6 @@
 	 end
       end
    end
-
-// synopsys translate_off
-initial begin
-   #10;
-   vid_clk_rst = 1;
-   #200;
-   vid_clk_rst = 0;
-end
-// synopsys translate_on
-
 endmodule


So, I interpret that to mean that the rest of the file is intended for
synthesis in some way, based on the comment pragma. I grepped for
anything using that output pin and came up with nothing, so it seems
safe to play with.  As far as I understand things, that sort of code
is bad style, someone might forget to test or code for the
initialisation of the pin if they're only testing in a simulator,
since the initial block takes care of it.

And yeah, that memory file is short, at least.  As I've said, I don't
really know enough about the code to know where I should be helping at
this point (still planning on writing tests though), but at least I'm
more comfortable with Verilog than I was 2 weeks ago.