[Open-graphics] CPU fetch stage

[Robert Fitzsimons]

> // Cause branch
> input [1:0] branch_condition;
...
>   case (branch_condition)
>       0: do_branch = 0;                       // no branch
...
>       7: do_branch = !bneg && !beqz;          // reg > 0
>   endcase

Just a quick comment.  Should the type of branch_condition not be [2:0]?
The case statement has 8 values which would require 3 bits.

Othere then that I have a high level idea of how the stage works, but I'm
still very much a newbie when it comes to verilog.

Robert