[Open-graphics] Documenting Hardware Design Process

[Attila Kinali]

On Wed, 28 Nov 2007 09:33:56 +0100
"Viktor Pracht" <ViktorPracht at gmx.de> wrote:

> > > 4) Verilog model --Icarus--> netlist --(OPAQUE contract service)--> ASIC
> > > graphics card is directly usable (this isn't really a "development
> > > cycle" because it takes months and close to a million dollars each
> > cycle).
> > 
> > Remove Icarus and netlist from that.  We'd probably have to buy a
> > license for one of the really expensive tools like Cadence's Build
> > Gates or Synopsys Design Compiler.  We would use that and provide the
> > netlist to the fabricator who would be responsible for P&R.
> 
> What can the really expensive tools do that Icarus can't?

They can actually synthesize our HDL code. There is currently no
OSS solution for either FPGA or ASIC synthesis.

			Attila Kinali
-- 
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But blest in my name forever this stream that stanched my thirst!
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