[Open-graphics] Documenting Hardware Design Process

[Timothy Normand Miller]

On 11/28/07, Attila Kinali <attila at kinali.ch> wrote:
> Moin
>
> On Tue, 27 Nov 2007 17:28:52 -0500
> "Timothy Normand Miller" <theosib at gmail.com> wrote:
>
> > Then
> > you can back-annotate the logical netlist with timing information that
> > you get from P&R.  If you simulate the original Verilog code, that's
> > called an RTL-level simulation.  If you simulate the back-annotated
> > netlist, that's called a gate-level simulation.
>
> I beg to differ. Simulating a back-annotated netlist is one
> way of doing timing verification, but it is not a gate level
> simulation. Gate level simulation means that you synthesized
> your design in to a gate level description and simulate this
> description to verify that the synthesizer did the conversion
> correctly.

I don't think we disagree.  I just think my description was incomplete
and sloppy.  Sorry about that.

-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project