[Open-graphics] Documenting Hardware Design Process

[John Griessen]

Timothy Normand Miller wrote:

> The really expensive tools are smart.  Icarus, Synplicity, ISE's
> synthesizer, and other basic ones like that aren't; they just make the
> most direct translation from Verilog to technology cells.  Then it's
> up to P&R to make it fit.  The smart tools look ahead, consider timing
> earlier in the process, and they'll refactor your logic to meet
> constraints. 

I took a Synopsys PrimeTime course where they also showed us their latest automation
as of 2002, and it was taking a global routing timing simulation first cut
and using that to place blocks, then doing its best sim of the delays...
pushbutton chip arranging.   They charge so much for that, that few buy it
and just iterate through human placements until they get good numbers,
(going for best max clock speed with a safety margin above spec vs. area used)

That way is Wall Street driven only.

John Griessen