[Open-graphics] Re: gEDA-dev: Problem with OGD1: Can anyone advise on good low-jitter

[John Griessen]

Timothy Normand Miller wrote:

> Unfortunately, it could take quite a long time for us to find
> suppliers of clock generators, get samples, wire them up and test
> them, etc., so we just need find out if someone out there already has
> the right answer or knows where to look for it.


You could try this PhD student researching Variable Fractional Period Clock Synthesis:
http://www.grm.polymtl.ca/~pontika/

He'll probably spit out something fast if hirable... I just noticed his "interests" page
searching yesterday...  don't know any more about him.

Your FPGA plus some cheap analog (sigma delta style) and switch drivers could make a smoothly
timed PLL clock synced as you like it -- I bet.

JG