[Open-graphics] Interested hacker

[Kenneth Østby]

We're even earlier than that.  At the moment, we're working on getting
> the board ready to sell.  Then we need to get the RTL properly
> organized so that people can do dumb framebuffer.  Then VGA's next on
> the agenda.
>
> Can we interest you in some of these things?


Sure. Sitting on my hands just waiting for you to finish all this would be
cruel wouldn't it? ;)

What are the people working on atm., and is there anything in special I
should focus/read up on ?

> Are there any forms of dependency graphs over work to be done found
> anywhere
> > on the wiki ?
>
> No, but this sounds like a wise thing to make.  Can you help with
> this?


I'll do some browsing through the documentation and mails, and see if I can
get something up on the wiki.


Oh, yeah, documentation is something we need more of.  :)


What ? Deja Vu.


If you can design real logic in VHDL, then you can do the same in
> Verilog.  Moving from either language to the other requires some
> adjustment, but not at any fundamental level.


I've been through the tutorials on the page, and I grasp the concepts,
so it shouldn't be all that hard. Although my experience is as a researcher,
so I've always focused my hw-skills on "fast, make it work" ,
instead of "make it work fast". :)

Kenneth
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