[Open-graphics] Need help with clock_gen.v

[Michael Meeuwisse]

I'd like to help, but I'm somewhat busy atm. Which signals are  
causing errors? If I had to guess it'd be divisor1_cur & divisor1_out  
being resetted in the wrong process. If so, I can easily fix his, but  
don't have the time right now to start up a machine with Webpack to  
synthesize.

On 3 Jun 2008, at 18:47, Timothy Normand Miller wrote:
> Could I get some help with the glock generator for video?
> vid_ctl/clock_gen.v has some signals that are assigned in multiple
> processes, so it's not synthesizable.  Also, Howard and Kenneth wrote
> a simple divider in lib/divider.v that could be used as part of the
> process.  Moreover, I may be able to get some existing code from
> Howard for this that can be adapted.

Also good if that works better than this.

Cheers,

Michael
www.projectvga.org