[Open-graphics] Need someone to contact Lattice on our behalf to get past a roadblock

[Timothy Normand Miller]

This is holding us up, and I was hoping I could get someone to contact
Lattice for us.  This is what Howard wrote:

We are having trouble meeting the PCI hold time
requirement on one of our designs. The problem
is the delay on the PCI clock from the input
pin through the clock buffer to the clock net.
Right now, this delay totals 3 ns, due in large
part to routing delay from the clock PAD to the
clock buffer.

We have another larger design that works and uses
the same clock pin. The delay from clock pad to clock
buffer is about half as much as in the new design.
We think this is because it seems to be using a
different clock buffer to that used in the new design.

Is there any way we can steer the Place and Route tool
to use a specific clock buffer ? Maybe that way we can
get the new design to look like the old one and meet
PCI hold time.





-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project