[Open-graphics] Please help: Video controller: Synthesis warnings that should be fixed

[Timothy Normand Miller]

On Tue, Jun 17, 2008 at 3:06 PM, Timothy Normand Miller
<theosib at gmail.com> wrote:
> On Mon, Jun 16, 2008 at 2:57 PM, Nicolas Boulay
> <nicolas.boulay at gmail.com> wrote:
>
>>
>> Can't you use a pipeline ? Duplicate only the last fifo stage ? Or
>> sometime, in a FSM, you could create a specific register for the bit
>> in the critical path. So you avoid any output decoding logic.
>>
>
> I tried a number of options, but each one would violate the timing
> constraints in some way.  Part of the problem is that I'm trying to
> run some of the logic at 190MHz, which is hard to meet under any
> circumstances.  For the moment, I'm going to say screw it and
> implement four dedicated 67-bit-wide fifos.  Besides, it may be that
> the control logic I have been trying to use to shrink the fifo was
> itself large enough to offset the gain.  I'll find out after this
> synthesis run what happens to the utilization.  RIght now, we're using
> 18% of available slices.  If we run out of space later, we can revisit
> some of these things and find ways to shrink them.

Heh.  When I did that, the design got smaller.


-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project