[Open-graphics] How we compute video clocks

[Michael Meeuwisse]

On 5 Mar 2008, at 02:28, Timothy Normand Miller wrote:

> On 3/4/08, Michael Meeuwisse <mickeymeeuw at gmail.com> wrote:
>> Not an issue if we divide by 2N, right?
>
> I think you will want to have the odd numbers for more precise control
> over the frequencies you get.  Also, don't worry that the duty cycle
> isn't 50/50.  The DCM will fix that.

Ah, ok. In that case I don't see why not.

> You TOGGLE it every clock, which divides by 2.

Argh. I think I fixed it now.

>> I'll find some docs about what this feedback is all about. But a wire
>>  connecting CLK0 to CLKFB will do the trick?
>
> Yup.

I removed it again because of what André said.

>> Ok, this one I wasn't sure about:
>>         valid_divisor[1] <= divisor1 > 0 && divisor1 < 7;
>>  Is this syntactically correct? As in, if divisor is > 0 and < 7,  
>> will
>>  valid_divisor[1] end up being 1?
>
> Yes.
>
> BTW, only clock on clocks.  Then use 'if' to decide whether or not  
> to assign.

What do you mean with clock on clocks?

>>  Also, I'm not passing lots of signals I'm using as clocks through a
>>  BUFG or anything. Should I? Say, divisor0_out for example.
>
> The final clock output should go through a BUFG.

That would be out_clock, fixed that.

>>  Lastly I'm not sure if my naming convention is understandable. I
>>  personally don't really like the _reg bits. It just looks wrong :)
>
> I tend to use Hungarian-like notation only on module ports so that you
> can tell the direction from an instance (with pass by name) what the
> directions are.

Ok. Any suggestions to what I should call them instead?

Cheers,

Michael
www.projectvga.org

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