[Open-graphics] How we compute video clocks

[Timothy Normand Miller]

On 3/5/08, Michael Meeuwisse <mickeymeeuw at gmail.com> wrote:

>  > BTW, only clock on clocks.  Then use 'if' to decide whether or not
>  > to assign.
>
>
> What do you mean with clock on clocks?

Don't use a data signal as a clock.  Obviously, we're doing this in
the clock GENERATOR, but once we have the signal generated properly,
we connect it up to the clock distribution network (via a BUFG).  But
in general, for "always @(posedge X)", X should only be a clock
signal, not the output of some register or combinatorial logic.

This is related to the effects of gating a clock.  When the clock is
not gated, it comes straight from the clock tree, so you know what its
timing characteristics are.  But if you gate it, you cannot predict in
advance what the gate delay will be.  Synthesizers CAN deal with this
kind of clock skew, but they don't tend to do it well.  This is
problematic for a register being loaded at one clock phase and then
sampled at another.  Metastability can occur, but mostly, we just have
tighter timing requirements.  But worse things can happen.

>  > I tend to use Hungarian-like notation only on module ports so that you
>  > can tell the direction from an instance (with pass by name) what the
>  > directions are.
>
>
> Ok. Any suggestions to what I should call them instead?

Nothing yet.  It will take some time for this to be refined anyhow.

-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project