[Open-graphics] How we compute video clocks

[Michael Meeuwisse]

On 5 Mar 2008, at 21:16, Timothy Normand Miller wrote:
>
> What you want is the bridge bus clock, because this is a configuration
> register, set through making writes to PCI.  I think we may call it
> "bridge_clock" in the S3 top level.

I was more thinking that this clock might be 133MHz or 156.25MHz, so  
that I should reuse those. But if there's already a clock defined I  
would just include an extra input pin. However, when looking into how  
this would fit in the existing stuff I found out that the vid_control  
module is already tracking a bunch of registers and how to set them,  
so I just changed that one to contain the new bits. That meant also  
changing some other files so I attached a diff. vid_control,  
vid_wrapper and s3_top_level are affected.

Could someone (I think actually Patrick McNamara, you're the  
maintainer of most of these files correct?) have a good look at what  
I'm doing? Am I handling the outgoing clock signal correctly?

Cheers,

Michael
www.projectvga.org

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