[Open-graphics] reciprocal table

[Pieter Hulshoff]

On Tuesday 07 December 2004 17:17, you wrote:
> Pieter Hulshoff wrote:
> > On Tue, Dec 07, 2004 at 08:46:17AM +0100, Viktor Pracht wrote:
> >>>   case (x)
> >>>       0: y <= 0;
> >>>       1: y <= 65280;
> >>>       2: y <= 65025;
> >>
> >>EEK! Is it really the only way to create ROM in Verilog?
> >
> > I doubt it. I don't know the Verilog commands, but in VHDL you
> > could have the precompiler do this work for you, and just
> > create a FOR loop that for each value of x calculates this
> > value for you. I'm sure Verilog has similar commands.
>
> Is there an online reference for the precompiler?
> And does Xilinx ISE support it?

Hmm, perhaps precompiler isn't the correct word. The constants within a 
program will be calculated through by the compiler before it generates the 
logic out of the rest of the design. It's a part of the normal language 
(VHDL/Verilog). Basically what you do is define a constant array, in which 
each element gets the calculated value of the 1/1.m function. I'm sure 
Timothy can build this without any trouble.

Regards,

Pieter Hulshoff