[Open-graphics] Here you go: Fully-pipelinedfloating pointdividerin Verilog

[Timothy Miller]

Pieter Hulshoff wrote:
> On Mon, Dec 06, 2004 at 12:43:49PM +0100, Nicolas Capens wrote:
> 
>>Nice work! I think the most interesting result is that with 8 lookup bits 
>>and 17 mantissa bits, we can get 16 bits of accuracy for the reciproke. 
>>That adequate as far as I can tell. For what it's worth, we can say it's 
>>equivalent to ATI's 24-bit format, with one bit extra for improved rounding 
>>where possible.
> 
> 
> 17 mantissa bits will not work with the 18 bits signed multiplication, since we
> need the extra 1., unless we design around that problem (mathematically not
> _that_ difficult I guess). How about using the 9 lookup bits and 16 mantissa
> bits in stead? Any comparisons available between the two?


If we use a dedicated RAM block, that's 10 address bits and 18 data 
bits.  Adding in the extra math (a couple of adders) so that we can get 
that one extra bit of precision is probably not worth it, given the 
extra logic area plus the extra pipelining.

So what we get out are 16 bits of mantissa, one bit to indicate how to 
manipulate the exponent (only entry 0 will have it set), and the last 
bit might be useful as a sort of "hint" for bias if we want to try to 
limit the lost precision of the input in some way.  Dunno.