[Open-graphics] Here you go: Fully-pipelinedfloating pointdividerin Verilog

[Timothy Miller]

Timothy Miller wrote:

> 
> If we use a dedicated RAM block, that's 10 address bits and 18 data 
> bits.  Adding in the extra math (a couple of adders) so that we can get 
> that one extra bit of precision is probably not worth it, given the 
> extra logic area plus the extra pipelining.
> 
> So what we get out are 16 bits of mantissa, one bit to indicate how to 
> manipulate the exponent (only entry 0 will have it set), and the last 
> bit might be useful as a sort of "hint" for bias if we want to try to 
> limit the lost precision of the input in some way.  Dunno.


Oops... sorry.  That was redundant.  :)