[Open-graphics] Open Hardware Verilog Library - request for advice
attila at kinali.ch
Mon Nov 12 04:19:27 EST 2007
On Sun, 11 Nov 2007 15:48:40 -0500
"Timothy Normand Miller" <theosib at gmail.com> wrote:
> On 11/11/07, Attila Kinali <attila at kinali.ch> wrote:
> > I personaly do not like the "negation bar" in source code
> > as i either use positive logic (there is no need for negative
> > logic within a synchronus design) or have few explicit signals
> > for which it is clear by their name that they are negative logic
> > (which are at the interfaces to the outside world only anways).
> Let me expose for a moment my ignorance of some of the analog aspects
> of digital circuit design. What is the primary reason for so many
> negative logic signals? My best guess is that one of the logic levels
> draws more current, but I'm probably going down the wrong track.
Well, it is to some part historical and to some part by convention.
Most of it comes because we (arbitrarely) choose GND as the refernece
level and build electronics in a way that they measure voltage levels
against GND. Thus, as Reimar already mentioned, it is easier to pull
a reset low during power up and prevent the circuit from behaving
Ofcourse the same can be done with a positive logic reset and pulling
up, if the input circuit would be build to reference against Vcc instead
of GND. But as i said, we do (normaly) measure voltages against GND.
This is the part that comes by convention.
The other reason why bus signals are often negative logic is,
that they needed a wired-or using open collector resp open drain
circuits to drive them low. Historicaly NPN and N-channel transistors
had a higher current drive because they use electrons as current
carriers which have a higher mobility than holes. These days PNP
and P-channel transistors can be build with same speed/current drive
as their counter parts, so this reason does not hold anymore
(at least in "normal" electronics). But it became a convention
and thus is still used everywhere.
That said, none of these reasons hold within a digital CMOS circuit
because N and P channel FETs have to be balanced and thus using
positive logic is absolutely equivalent to negative logic
(given that the reset circuit works properly). And thus i prefere
the positive logic within designs because usualy they are easier
Praised are the Fountains of Shelieth, the silver harp of the waters,
But blest in my name forever this stream that stanched my thirst!
-- Deed of Morred
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