[Open-graphics] Problem with OGD1: Can anyone advise on good
Timothy Normand Miller
theosib at gmail.com
Fri Nov 30 13:49:05 EST 2007
On 11/29/07, James Richard Tyrer <tyrerj at acm.org> wrote:
> Timothy Normand Miller wrote:
> > Sorry about the cross-post. We're -><- THIS close to getting OGD1
> > done, with artwork in the hands of board makers who are working on
> > quotes, and we've discovered a problem that could make the video
> > output unacceptable.
> Also, please consider if the jitter can be reduced.
> Is this measured jitter or the devices spec?
Measured. The jitter we're observing is much worse than the spec.
That seems to be a common problem, and we're also dealing with types
of jitter that specs don't even mention. For instance, low-frequency
jitter tends not to be a problem when you're all digital, but it's
something you can see on an analog monitor.
> I presume that these jittery clocks are being generated by a PLL
> frequency synthesizer in the FPGA.
They're DCMs, not PLLs. They're "all digital."
> This specifically mentions power supply noise and ground bounce.
> Basically, this comes down to reducing the noise on the PLL VCO input
> power by adding a regulator or improving the bypass capacitor (which can
> mean adding parallel small capacitors) and a larger ground buss and
> proper routing of the output clock ground to the PLL input ground. It
> is very difficult to bypass the ground because the bypass would need to
> have much less series inductance than the ground lead -- easier to make
> a larger ground lead -- although you can do this if we have a negative
I described what's going on in an earlier email. We have all the
power smoothing that we should need on the FPGA. What's mucking with
the DCMs is activity inside of the FPGA, and the DCMs aren't properly
isolated. We can't control that.
> Which IC is the relevant clock for the generation of the pixel clock (Y2
> or Y3 perhaps). Where does the power to operate it come from? Which
> power bypass capacitors are immediately next to the oscillator?
If you take the crystal output and use that directly as a clock, it's
just perfect. It's when you connect it to a DCM and give it a
multiplier and divider that you see jitter introduced. All the PCB
stuff is the same in both cases. It's only whether or not the clock
goes through a DCM. For things that are completely internal, the DCMs
work fine. Say your drawing engine needs to run at 100MHz, but you're
getting that from a 180MHz source. Well, there'll be lots of jitter
in that 100MHz clock, but it doesn't matter since everything's being
driven by that same clock. As long as you account for the phase
variance (by adding it to the worst-case prop delay), everything works
just fine. It's when we use a jittery clock to interface with things
like memory chips and video devices that we run into problems.
Timothy Normand Miller
Open Graphics Project
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