[Open-graphics] Re: Some small changes
mark.marshall at csr.com
Fri Nov 5 13:57:49 EDT 2010
On 03/11/2010 02:44, Patrick McNamara wrote:
> On 11/02/2010 07:13 AM, Mark Marshall wrote:
>> A change to how interrupts are dealt with. I will add the PCI defined
>> disable interrupt bit and the interrupt status bit to config space. I
>> also plan to modify the way in which the clear_interrupt register will
>> work. From a lot of experience with interrupts in embeded platforms
>> this is how it should work:
>> There is a set number of different interrupt sources, all multiplexed
>> onto the same interrupt. We have a number of registers that have the
>> same structure (one bit per source), these registers are called
>> "int_status", "int_mask" and "int_clear".
>> If any interrupt source triggers (there's a hotplug event of
>> whatever), then the corisponding bit in "int_status" gets sets. This
>> always happens.
>> If "(int_status & int_mask) != 0" then we raise an interrupt to the host.
>> If a value is written to "int_clear", then the ones in the value
>> written clear those interrupt sources (and only those). (This is often
>> written as W1C in hardware specs.)
>> The host will perform exactly this sequence to ack the interrupts.
>> temp = int_status;
>> int_clear = temp;
>> This scheme produces "race-free" operation. Almost every other scheme
> Sounds sane to me. I haven't looked at how current PCI interrupt
> handling is done in OGD1, so I'll defer to your suggestion.
I've now done this - 745 & 746
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